Circular buffers are commonly found in digital signal processors, such as, for example, the Analog Devices ADSP 2181 or the Philips REAL DSP, where a memory segment can be addressed after modifying the address by a modulo operation. In such cases, the data is fetched in one cycle, stored in a register, and used as an operand in the next cycle. In such examples, the circular buffer is maintained in memory, and in order to process the data stored therein, or properly write new data thereto, memory read/write instructions must be used. Such instructions increase computing overhead, the complexity of the instruction set, as well the additional time taken by the memory handling. Besides such conventional uses of circular buffers, there are no designs known to exist that allow modulo addressing of a register file directly, or the use of modulo addressing in an array processor. Modulo addressing allows the facilitation of a sequentially linked series of data elements, where when the end of the series is reached, the sequence wraps around to the beginning. As an example, in a circular buffer of N data storage positions, numbered say, from 0 to N−1, where the system is set up such that the next storage position from a given position X is defined as X+1, modulo addressing allows (N−1)+1=0 (mod N), thus achieving the wrapping effect. Alternatively, a circular memory could be set up such that the next memory position I from a given position X is defined as X−1, and then 0−1=(N−1) (mod N), again achieving the wrapping effect.
In the context of a multi-processor, or an array processor designed for high-throughput repetitive signal processing, such as that disclosed in copending U.S. patent application Ser. No. 09/968,119, the individual cell has limited or no memory addressing capability. In such case, maintaining a circular buffer in memory is more than an added complexity to deal with; it is simply impossible.
Thus, what would facilitate a delay line or the like in the cell of such an array processor, i.e., the equivalent to the implementation of a circular buffer in memory, is the facility to modulo address the actual registers where data is stored while under processing. There are no known designs which allow modulo addressing in a datapath instruction.
What is needed to solve these lacunae in the conventional art, is a method and apparatus for modulo addressing of registers in a datapath instruction. Such a method would allow a processor to maintain a sequential series of data, such as a delay line, in the actual registers themselves, thus obviating the need for memory handling capability.